Flash memory is a commonly used type of non-volatile memory in widespread use as mass storage for consumer electronics, such as digital cameras and portable digital music players for example. The density of a presently available Flash memory chip can be up to 32 Gbits (4 GB), which is suitable for use in popular USB Flash drives since the size of one Flash chip is small.
The advent of 8 mega pixel digital cameras and portable digital entertainment devices with music and video capabilities has spurred demand for ultra-high capacities to store the large amounts of data, which cannot be met by the single Flash memory device. Therefore, multiple Flash memory devices are combined together into a memory system to effectively increase the available storage capacity. For example, Flash storage densities of 20 GB may be required for such applications.
FIG. 1 is a block diagram of a prior art Flash memory system 10 integrated with a host system 12. Flash memory system 10 includes a Flash memory controller 14 in communication with host system 12, and multiple non-volatile memory devices 16. The host system will include a processing device such as a microcontroller, microprocessor, or a computer system. The Flash memory system 10 of FIG. 1 is configured to include one channel 20, where memory devices 16 are connected in parallel to channel 20. Those skilled in the art will understand that the memory system 10 will have any number of memory devices connected to it.
Channel 20 includes a set of common buses, which include data and control lines that are connected to all its corresponding memory devices. While not shown, each memory device is enabled/disabled with a respective chip select signal provided by Flash memory controller 14. The Flash controller 14 is responsible for issuing commands and data, via the channel, to a selected memory device based on the operation of the host system 12. Data read from the memory devices is transferred via the channel back to the Flash memory controller 14 and host system 12. Flash memory system 10 is generally referred to as a multi-drop configuration, in which the memory devices 16 are connected in parallel with respect to channel 20.
In Flash memory system 10, non-volatile memory devices 16 are identical to each other, and are typically implemented as NAND Flash memory devices. Those skilled in the art will understand that Flash memory is organized into banks, and each bank is organized into blocks to facilitate block erasure. Most commercially available NAND Flash memory devices are configured to have two banks of memory. Prior to a discussion of the operation of Flash memory system 10, a brief overview of a single NAND Flash memory device memory core is described.
FIG. 2 is a general block diagram of one bank of a known NAND Flash memory. Bank 30 is organized into k+1 blocks. Each block consists of NAND memory cell strings, having up to i+1 Flash memory cells serially connected to each other. Accordingly, wordlines WL0 to WLi are connected to the gates of each Flash memory cell in the memory cell string. A string select device connected to signal SSL (string select line) selectively connects the memory cell string to a bitline, while a ground select device connected to signal GSL (ground select line) selectively connects the memory cell string to a source line, such as VSS. The string select device and the ground select device are n-channel transistors. There are j+1 bitlines common to all blocks of bank 30, and each bitline is connected to one NAND memory cell string in each of blocks [0] to [k]. Each wordline (WL0 to WLi), SSL and GSL signal is connected to the same corresponding transistor device in each NAND memory cell string in the block. As those skilled in the art should be aware, data stored in the Flash memory cells along one wordline is referred to as a page of data.
Connected to each bitline outside of the bank 30 is a data register 32 for storing one page of write data to be programmed into one page of Flash memory cells. Data register 32 also includes sense circuits for sensing data read from one page of Flash memory cells. During programming operations, the data registers perform program verify operations to ensure that the data has been properly programmed into the Flash memory cells connected to the selected wordline. Programming within a block typically starts at the page corresponding to WL0, and proceeds sequentially up to WLi to fill the present block. Then programming continues with WL0 of a new block. Within a device, blocks are programmed in sequence.
Returning to the Flash memory system 10 of FIG. 1, there are specific issues that will adversely impact performance of the system. Some are physical while others are architectural.
The configuration of Flash memory system 10 imposes physical performance limitations. With the large number of parallel signals running across the system, the signal integrity of the signals they carry will be degraded by crosstalk, signal skew, and simultaneous switching noise (SSN). Power consumption in such a configuration becomes an issue as each signal track between the flash controller and flash memory devices is frequently charged and discharged for signaling. With increasing system clock frequencies, the power consumption will increase as well.
From an architectural perspective, programming operations will take too much time. A primary function of the Flash controller 14 is to manage the writing of data to the memory devices in the system. In the Flash memory context, writing of data is more commonly referred to as programming data. There are two significant issues related to Flash programming. First, Flash programming is slow relative to volatile memories such as DRAM and SRAM, and other non-volatile memories such as hard disk drives. Programming data to Flash memory cells requires high voltages and a stepped programming sequence to obtain a tight programmed threshold voltage distribution. In a NAND Flash memory device having two banks of memory, two pages of data are concurrently programmed, one for each bank. Since there is only one data register per bank, further programming operations must wait until the current pages have been successfully programmed. Therefore, programming large quantities of data to the Flash devices 16 may require a significant amount of time.
A second issue with the conventional Flash memory system 10 is the linear file structure of the program data. FIG. 3 is an illustration of the conventional file structure for a Flash memory system 50 having four memory devices. In FIG. 3, each memory device 52, 54, 56 and 58 has a total of n physical pages of storage space, which are divided among any number of blocks. In the presently shown example, it is assumed that the n pages are divided equally between two banks. Most Flash memory systems will store a data file consisting of a number of data pages, linearly within one memory device. For example, the first page of the data file is stored in Page 0 of device 52, and successive data pages are progressively stored in subsequent pages. Once device 52 is full, then further data files to be stored in system 50 starts at Page 0 in device 54, and so forth. Arrow 60 shows the storage pattern of data being written to the Flash memory system 50.
This linear file structure coupled with the relatively long programming time per page of the data file per memory device, results in a Flash memory system that requires significant time to store data. Another issue which is related to the linear file structure is device reliability, and more specifically, program/erase wearing of one memory device relative to the other memory devices in the system. Program/erase wearing refers to a progressive degradation of a Flash memory cell due to cumulative program and erase operations. The effect of such cumulative program and erase operations is the alteration of the program and erase characteristics of the memory cell beyond optimal parameters. When memory cells are degraded, higher program and erase voltages are needed to program or erase the memory cells to the desired threshold voltages. Eventually, the memory cells will fail to function properly. This is the reason that Flash memory are rated for a limited number of erase-program cycles, which is between 10,000 and 100,000 cycles.
If for example, the first memory device 52 in FIG. 3 endures more program and erase cycles than any of the other memory devices, memory device 52 will likely fail before the others. When memory device 52 fails, the entire system 50 is no longer usable since the memory devices are packaged together and replacement of a single memory device is impractical. This is an unfortunate waste of memory devices, as the remaining devices in the system are still useful and may have significant life left.
An inherent technical architecture of most Flash memory is that the smallest unit of memory which is erasable is a block of memory. This means that if even one page within the block is to be modified, the entire block must be re-programmed along with the new page. This is referred to as block re-programming, which requires significant programming time and hence negatively impacts performance of the system.
Therefore, presently known Flash memory systems have slow throughput for programming data, and due to the unequal program and erase wearing across the devices, the entire system will have a lifespan limited to the first memory device to fail.
It is, therefore, desirable to provide a high speed Flash memory system architecture having a scheme for maximizing the lifespan of the system.